I am proud to share that I was elected the Vice Chair of the RISC-V J-extension (so-called J-ext) Task Group 🙂 My last 3-4 years of work on the RISC-V architecture were quite fruitful:
- I am an author of RISC-V Pointer Masking extension:
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf - I am one of the Contributors to RISC-V Control Flow Integrity (CFI):
https://github.com/riscv/riscv-cfi/blob/main/riscv-cfi.pdf - I help driving I/D consistency extension
- HWASAN and Memory Tagging (MTE) on RISC-V
- I found a critical bug in the RISC-V architecture (not in the implementation of a specific processor) that got CVE-2021-1104. Among other things, I talked about this vulnerability in 2021 at the DefCon 29 conference
Thanks,
Adam
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